Internship at Electrolux GC&T: ” Anomaly detection in embedded electronic systems”

Pubblico questa proposta di stage/tirocinio con tesi presso il team Global Connectivity and Technology (GC&T) della Electrolux (Porcia). La proposta di tirocinio è principalmente orientata a studenti della laurea magistrale in Informatica o Computer Science, ma anche studenti della laurea triennale adeguatamente motivati possono fare domanda. Se siete interessati, contattatemi via email. 

In the IoT era, household appliances play a relevant role inside connectivity ecosystems thanks their diffusion on the market and their potential in terms of computational power compared to simple sensors. More than that a specific focus is on connectible appliances exploitation as a channel for cloud resourced applications. Connectible appliance has to be considered as an embedded electronic system with the typical computational capability of a household appliance plus a communication node.

The goal of this internship is to design and develop suitable techniques to monitor specific processes of the above mentioned embedded system (in particular the communication node), in order to promptly detect anomalies caused by unexpected faults or external attacks. Your research tasks will be integrated with running projects aimed at developing and validating solutions in the field of electronic embedded systems.

Main duties:

  • Literature review
  • Experimental phase:
  • Reference HW-FW analysis, Process characterization
  • Design of a potential solution
  • Development on a reference HW and FW
  • Final report.

The student will carry over the research tasks in Electrolux facility (GC&T Porcia (Pn)), under the responsibility of an academic scientific reference and an Electrolux tutor, within the collaboration between University of Udine and Electrolux.


One year industrial research position at the University of Udine (deadline: 10 Oct 2018)

One year industrial research position at the University of Udine about
Modelling and performance evaluation of train on-board networks
Funded by EU FSE program HEaD

Deadline for application: October 10, 2018, 11:30.


Nowadays trains feature advanced on-board information networks which are used both for essential services and for additional (infotainment) services, and must guarantee an adequate level of service quality.
Designing, implementing and validating these networks, respecting precise qualitative and quantitative constraints (bandwidth, delay, fault tolerance, etc.) is complex and error-prone.
The objective of this project is to define practical methods and solutions for modelling train on-board networks, both in the topological and in the quantitative aspects, with the aim to simulate and predict their behavior in various traffic conditions before implementation and deployment. These solutions will use tools and technologies currently developed within the academic community, such as quantitative simulators and model checkers.


Candidates must have a Master degree in Computer Science or Computer Engineering (PhD is not required but appreciated), and a good background in network performance analysis, especially in tools for network simulation / evaluation. Good programming skills will be appreciated.

Working conditions

The selected candidate will work mainly at the Department of Mathematics, Computer Science and Physics (DMIF), of the University of Udine (Italy), in strict cooperation with VDS Rail, a leading industry of the sector.

The total net salary is 20.382,00 euro.

For more information please contact Marino Miculan (

More details about the applications are at the official call.

Qualche statistica su Reti di Calcolatori 2017-18

Come di tradizione, adesso che si è chiuso anche l’ultimo appello di Reti di Calcolatori per l’A.A. 2017-18 possiamo fare qualche veloce analisi.

Nei cinque appelli del 2018 si sono iscritti ad almeno un appello 162 studenti (+13 rispetto al 2017; 8,7%), per complessive 310 iscrizioni (+49; +18,7%).
Si sono registrate 245 presenze agli scritti (+41; +20%), e sono stati consegnati 202 compiti (+55; +37,4%).
Di questi, dopo l’eventuale esame orale sono stati verbalizzati 97 esami (+19; +24,3%) (c’è molta variabilità tra un appello e l’altro).
Il voto medio è stato 21,3; il voto massimo è stato 26.

Quindi possiamo dire che:

  • lo Studente che si iscrive all’esame scritto ha una probabilità di registrare il voto pari a 97/310=31,29% (+1,41%), quindi lo Studente deve iscriversi mediamente 1/0,3129 = 3,2 volte;
  • lo Studente che consegna lo scritto ha una probabilità di registrare il voto pari a 97/202=48% (-5,1%), quindi lo Studente deve consegnare mediamente 1/0,48 = 2,1 volte;
  • la probabilità che lo Studente superi l’esame di Reti di Calcolatori in un anno accademico è pari a 97/162=59,8% 52,34% (+7,5%);
  • il “backlog” è di 162-97=65 studenti (-6).